The Full Timetable
Timetable of AY 2007/2008 Semester 1
Currently only have Wednesday mornings and Friday afternoons free, with some of the Thursday afternoons and a very few Wednesday afternoons free. Well, I wanted to get one of the EE2009 (Signals) tutorial slots on Wednesday, 12.00pm to 1.00pm, but the tutorial slots were oversubscribed, so I was being allocated to one of the EE2009 tutorial slots on Friday, 11.00pm to 12.00pm. Ok, so that means I'm having lunch outside NUS after 2.00pm on Friday.
Among the 3 EE modules that I'm taking, EE2005 (Electronics), EE2006 (Digital Design) and EE2009 (Signals), I feel that EE2009 is one of the most difficult EE modules I'm taking this semester. It's very mathematical, and it's difficult to interprete those signals into Mathematics. A lot of things to digest, and even if I mug hundreds or thousands of times, if you don't know means don't know, unless you are expert in Mathematics, and are able to model those questions into some Maths formula. Some more the exam is open book, so what's the point of mugging? EE2005 is somewhat reasonable, and somewhat difficult, depends on the topic. EE2006 is still reasonable, but heard that the VHDL programming can be difficult...
Past Timetable
Here are my past timetable.
AY 2006/2007 Semester 1
AY 2006/2007 Semester 2
Currently only have Wednesday mornings and Friday afternoons free, with some of the Thursday afternoons and a very few Wednesday afternoons free. Well, I wanted to get one of the EE2009 (Signals) tutorial slots on Wednesday, 12.00pm to 1.00pm, but the tutorial slots were oversubscribed, so I was being allocated to one of the EE2009 tutorial slots on Friday, 11.00pm to 12.00pm. Ok, so that means I'm having lunch outside NUS after 2.00pm on Friday.
Among the 3 EE modules that I'm taking, EE2005 (Electronics), EE2006 (Digital Design) and EE2009 (Signals), I feel that EE2009 is one of the most difficult EE modules I'm taking this semester. It's very mathematical, and it's difficult to interprete those signals into Mathematics. A lot of things to digest, and even if I mug hundreds or thousands of times, if you don't know means don't know, unless you are expert in Mathematics, and are able to model those questions into some Maths formula. Some more the exam is open book, so what's the point of mugging? EE2005 is somewhat reasonable, and somewhat difficult, depends on the topic. EE2006 is still reasonable, but heard that the VHDL programming can be difficult...
Past Timetable
Here are my past timetable.
AY 2006/2007 Semester 1
AY 2006/2007 Semester 2
water source from MiZ @ 4:10 PM
0 Comments:
Post a Comment
<< Home